1. Field of the Invention
The present invention generally relates to the design of semiconductor chips and integrated circuits, and more particularly to a method of identifying different portions of an integrated circuit design which may be handled differently during optimized placement of the circuit components in a layout.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins, including information about the various components such as transistors, resistors and capacitors. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then run through a dataprep process that is used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to etch or deposit features in a silicon wafer in a sequence of photolithographic steps using a complex lens system that shrinks the mask image. The process of converting the specifications of an electrical circuit into such a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction. Given a netlist N=(V, E) with nodes (vertices) V and nets (edges) E, a global placement tool obtains locations (xi, yi) for all the movable nodes, such that the area of nodes within any rectangular region does not exceed the area of cell sites in that region. Though some work has looked at general Steiner wirelength optimization, placers typically minimize the half-perimeter wirelength (HPWL) of the design. Modern placers often approximate HPWL by a differentiable function using a quadratic objective.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to repower gates (changing their sizes), insert repeaters (buffers or inverters), clone gates or other combinational logic, etc., so the area of logic in the design remains fluid. However, physical synthesis can take days to complete, and the computational requirements are increasing as designs are ever larger and more gates need to be placed. There are also more chances for bad placements due to limited area resources.
As technology scales beyond the deep-submicron regime and operating frequencies increase, a new style is emerging in the design of integrated circuits referred to as hybrid designs, which contain a mixture of random logic and datapath (standard cell) components. In random logic, a given logic function or cone may have cells randomly distributed in different rows to satisfy the placement constraints, with no particular boundaries for any set of cells. In contrast, datapath logic usually has more regular boundaries. Datapaths are often composed of bit slices (bit stacks) where logic for each bit typically has the same structure. For example, an 8-bit rotator will have 8 individual bit slices with the same structure. Datapath logic has traditionally been placed manually, i.e., a custom design, as seen in the example of FIG. 1A. The manually placed datapath logic (macro) 1 has a plurality of cells that have been positioned to receive select signals along the top and bottom rows as indicated by the horizontal arrows 2. Each bit slice is neatly arranged in aligned stacks as indicated by the vertical arrows 3. There has been a significant effort in recent years to include the placement of datapath logic in the automation process, particularly for hybrid designs which also contain random logic. However, placement formulation for datapath logic is generally different than that for random logic. Random logic placers ignore this aspect of hybrid designs, which can lead to major wirelength and congestion issues with state-of-the-art devices. FIG. 1B illustrates the same datapath logic as FIG. 1A but now it is an automatically placed design 4 using a random logic placer. The same select lines 2 are used for random layout 4, but the bit stacks are no longer aligned, as indicated by the zigzag arrow 5.
Methods have accordingly been devised for automatically extracting bit stacks from a netlist. Identifying the structures ahead of time allows tools to reduce the overall wirelength by making placement structure-aware. Once a bit stack is known, it can be passed to a datapath placer for improved wirelength reduction. Bit stack extraction techniques include maintaining the datapath structure from the high level description (VHDL), template based extraction, name based extraction, and network-flow based searching. In the first of these techniques, hard constraints are imposed on the design using the original datapath structure to limit the datapath optimization. In template based extraction, a template is provided as an input and used in pattern matching to generate bit-stack candidates. Name based extraction relies on the prior assignment of names or labels to cells, and tries to match names together to build the bit stacks. Network-flow based searching generates clusters based on latches or primary inputs/primary outputs. For a given cluster, input fan-out cones are searched, output fan-in cones are searched, and gates marked in both searches are provided as candidates for the bit stack. Disjoint paths between the inputs and outputs are identified such that the maximum number of gates are covered, and a flow network is constructed to capture the constraints. The min-cost solution corresponds to the maximum number of gates.